1. Field of the Invention
This invention relates generally to high speed logic circuitry and, more particularly, to high speed transistor transistor logic (TTL) circuits having an improved output pulldown circuit.
2. Description of the Prior Art
Prior art TTL logic circuits include at least one interstage current drive transistor coupled between an output semiconductor device such as a transistor and a source of binary input logic signals. Typically, the output device is either in saturation or is turned off depending upon the conditions of the binary logic input signals.
The output terminal of a TTL circuit is generally coupled to the collector of an output transistor the potential of which may be one of two distinct logic levels. When the output transistor is in or near saturation, the output terminal will be at a binary zero level using positive logic. When the output transistor is turned off, its collector voltage increases and the voltage at the output terminal will rise from a binary zero level to a binary one level.
The time it takes for the output transistors to turn off depends to a large extent on the time required for the base charge to be removed or diverted from the base of the output transistor. This was accomplished using a single pulldown resistor connected between the base of the output transistor and some reference potential. When it was desired to turn the output transistor off, the conductive path through the pulldown resistor provided the necessary path for removing base drive from the output transistor and terminating its conduction.
The problem associated with this technique is that current will begin to flow in the pulldown resistor prior to the time that the input signals applied to the TTL circuit reach a level sufficiently high to drive the output transistor into or near saturation and switch the circuit output terminal from one to the other of its two states. This current flow in the pulldown resistor produces a corresponding unwanted reduction in the DC output voltage level in the absence of a proper binary signal condition at the input of the circuit. Thus, if extraneous noise signals are coupled to the input of the TTL circuit which is equipped with only a pulldown resistor to discharge the output device, corresponding unwanted fluctuations in the output voltage level will be produced when current flows in the pulldown resistor.
To improve the input/output transfer characteristic of TTL logic circuits and to provide a high degree of noise immunity, a bypass network may be coupled between the output device and a reference potential. The bypass network provides good turnoff drive for the output device and decreases spiking in the output signals for input voltages which are not sufficiently high to drive the output device into or near saturation. Such an arrangement is shown and described in U.S. Pat. No. Re. No. 27,804 reissued Oct. 30, 1973 entitled "Transistor-Transistor Logic Circuits Having Improved Voltage Transfer Characteristics" and assigned to the assignee of the present invention. This arrangement, however, is intended for use in circuits comprising high breakdown transistors (i.e., over 12 volts). However, advances in integrated circuit technology have resulted in integrated circuits of increased density having shallower junctions and/or higher doping concentrations all of which tend to reduce the breakdown voltage to, for example, 6 volts. If a voltage exceeding the breakdown voltage is applied to the output terminal of a TTL circuit equipped with the bypass circuit of U.S. Pat. No. Re. No. 27,804, a leakage current will flow from the collector of the output transistor through its base and into its emitter causing the output transistor to breakdown or snap back and possibly result in a latchup situation.